1. Field of the Invention
The present invention relates to a semiconductor device and a method of producing the semiconductor device and more particularly to a semiconductor device comprising stacked and electrically connected semiconductor chips having LSIs and a method of producing the semiconductor device.
2. Prior Art
In recent years, inorder to make LSI semiconductor devices lower in cost and smaller in size, a semiconductor device has been proposed wherein semiconductor chips having LSIs provided with functions different from one another or semiconductor chips having LSIs formed by processes different from one another are joined with one another in a face-down method.
The above-mentioned conventional LSI semiconductor device will be described below referring to FIG. 16. First, on a first semiconductor chip 110, the inner electrodes (the first inner electrodes) 111 of the first semiconductor chip and bonding pads 112 are formed. In addition, on the first inner electrodes 111, the barrier metals (the first barrier metals) 113 of the first semiconductor chip are formed. Furthermore, the barrier metals (the second barrier metals) 122 of a second semiconductor chip 120 on the inner electrodes 121 (the second inner electrodes) of the second semiconductor chip 120 are electrically connected to the second inner electrodes 121 on the second semiconductor chip 120 via bumps 123 made of solder. Moreover, the space between the first semiconductor chip 110 and the second semiconductor chip 120 is filled with an insulating resin 130, and the first semiconductor chip 110 and the second semiconductor chip 120 are integrated with each other by the bumps 123 and the insulating resin 130.
The first semiconductor chip 110 is secured to the die pad 131 of a lead frame by using a die bonding resin 132. The bonding pads 112 of the first semiconductor chip 110 are electrically connected to the outer leads 133 of the lead frame via bonding wires 123. The first semiconductor chip 110, the second semiconductor chip 120, the bonding wires 133, the die pad 131 and portions of the outer leads 133 are packaged with a sealing resin 135.
A method of producing the above-mentioned semiconductor device will be described below referring to FIGS. 17A to 17D. First, as shown in FIG. 17A, the solder bumps 123 are formed on the inner electrodes 121 of the second semiconductor chip 120 by electroplating. Regarding the forming of the solder bumps 123, after the second barrel metals 122 are formed on the wafer for the second semiconductor chip 120 by vapor deposition, a bump pattern is formed by using a resist, and the bumps 123 are formed by electrolytic solder plating. Next,the second barrier metals 122 are melted and removed by wet etching, with the solder bumps 123 used as masks, and then the solder pumps 123 are subjected to reflowing so as to have a hemispheric shape. Next, as shown in FIG. 17B, the insulating resin 130 is applied onto the first semiconductor chip 110 when the first semiconductor chip 110 is in a wafer state, and the solder bumps of the second semiconductor chip 120 are aligned with the inner electrodes 111 of the first semiconductor chip 110. Next, as shown in FIG. 17C, the second semiconductor chip 120 is mounted on the first semiconductor chip 110. The solder bumps 123 are then melted by heating so that the inner electrodes 121 of the second semiconductor chip 120 are joined with the inner electrodes 111 of the first semiconductor chip 110 by soldering. Next, as shown in FIG. 17D, the first semiconductor chips 110 in the wafer state are individually separated. In the end, as shown in FIG. 16, the first semiconductor chip 110 is die-bonded to the die pad 131 of the lead frame, the bonding pads 112 of the first semiconductor chip 110 are connected to the outer leads 133 of the lead frame by wire bonding, and packaging is carried out by using the sealing resin 135.
However, the structure of the above-mentioned conventional semiconductor device and the above-mentioned method of producing the semiconductor device have the following problems, since the connection between the first semiconductor chip and the second semiconductor chip is carried out by soldering by using the solder bumps.
(1) Since the first semiconductor chip is stacked on the second semiconductor chip by the face-down method, chips can be stacked up to only two layers.
(2) Since the metal bumps are used when the first semiconductor chip is stacked on the second semiconductor chip, the chips may be damaged, and the semiconductor components of the chips may be broken.
(3) Since the solder is melted during joining, the solder spreads sideways. As a result, dimensional changes occur, whereby it is difficult to attain fine structures.
(4) Since the inner electrodes of the semiconductor chips are usually made of Al, it is necessary to form a metal film capable of easily diffusing with the solder, such as a metal film of Ti, Cu, Au or the like, on each of the Al electrodes in order to properly carry out solder joining. This results in higher cost.
(5) Since it is difficult to attain fine structures, the inner electrodes of the first and second semiconductor chips become larger in size, thereby having larger electrical load capacities. This increases delay in signal transmission between the first and second semiconductor chips and also increases power consumption.
Accordingly, the present invention is intended to provide a high-performance semiconductor device wherein a plurality of chips can be stacked without damaging the chips and minute connection is attained easily, and also intended to provide a method of producing the semiconductor device.
A semiconductor device in accordance with claim 1 of the present invention comprises a first semiconductor chip having outer electrodes and inner electrodes, anda second semiconductor chip having inner electrodes, the second semiconductor chip being stacked on the first semiconductor chip with a space provided therebetween, and the inner electrodes being electrically connected to each other, wherein through holes are provided in the inner electrodes of the second semiconductor chip, electrodes capable of being plated by electroless plating are formed on the inner walls of the through holes while being insulated from other electrodes, the second semiconductor chip is secured with an adhesive to the first semiconductor chip at portions other than the outer electrodes and the inner electrodes of the first semiconductor chip so that the inner electrodes of the first semiconductor chip are aligned with the inner electrodes of the second semiconductor chip, and the inner electrodes of the second semiconductor chip and the electrodes on the inner walls of the through holes are electrically connected to the inner electrodes of the first semiconductor chip by continuously extending metals having the same composition.
By forming the through holes in the inner electrodes of the second semiconductor chip and by stacking the first and second semiconductor chips by using the adhesive as described above, a plurality of chips can be stacked without damaging the chips. The electrodes formed on the inner walls of the through holes and capable of being plated by electroless plating are made of Cu, Ni, Au, Pt, Ag, Sn, Pb, Co, etc. The inner electrodes of the second semiconductor chip and the electrodes on the inner walls of the through holes are electrically connected to the inner electrodes of the first semiconductor chip by the continuously extending metal shaving the same composition. For this reason, instead of the conventional joining using solder bumps, the metal deposited directly on the inner electrodes by electroless plating is used for joining. Therefore, unlike the case of the conventional method, it is not necessary to form a metal for causing solder diffusion beforehand on the inner electrodes of the chips.
A semiconductor device in accordance with claim 2 is a semiconductor device in accordance with claim 1, wherein the diameter of the thorough hole in the inner electrode of the second semiconductor chip is made smaller than the half of the space between the first semiconductor chipand the second semiconductor chip. Since the diameter of the thorough hole in the inner electrode of the second semiconductor chip is made smaller than the half of the space between the first semiconductor chip and the second semiconductor chip, secure connection can be attained. In other words, since the growth of a film plated by electroless plating is usually isotropic, if the diameter of the thorough hole is not less than the half of the space, when the wall of the through hole makes contact with a plated film, i.e., a metal formed on the electrode, the through hole is not filled with a plated metal, whereby a plating liquid remains inside the electrode. Since this remaining liquid causes corrosion, the above-mentioned setting is carried out so that the plating liquid does not remain inside the electrode.
A semiconductor device in accordance with claims 3 and 4 is a semiconductor device in accordance with claim 1, wherein the second semiconductor chips, two or more in number, are stacked. Since the second semiconductor chips, two or more in number, are stacked, this structure is applicable to LSIs having numerous pins.
Amethod of producing a semiconductor device in accordance with claim 5, comprises a step of providing the through holes in the inner electrodes of the second semiconductor chip to be stacked on the first semiconductor chip, a step of forming insulating films on the inner walls of the through holes and the rear face of the second semiconductor chip, a step of forming electrodes capable of being plated by electroless plating on the inner walls of the through holes by electroless plating or vapor deposition, a step of bonding and securing the second semiconductor chip to the first semiconductor chip at portions other than the outer electrodes and the inner electrodes of the first semiconductor chip so that the inner electrodes of the first semiconductor chip are aligned with the inner electrodes of the second semiconductor chip with a space provided to the first semiconductor chip, and a step of electrically connecting the inner electrodes of the second semiconductor chip and the inner walls of the through holes to the inner electrodes of the first semiconductor chip by electroless plating.
As described above, the through holes are provided in the inner electrodes of the second semiconductor chip, the first semiconductor chip and the second semiconductor chip are bonded and secured to each other, and the inner electrodes of the second semiconductor chip and the inner walls of the through holes are electrically connected to the inner electrodes of the first semiconductor chip by electroless plating. Therefore, a plurality of chips can be stacked without damaging the chips. In addition, electrodes capable of being plated by electroless plating are formed on the inner walls of the through holes by electroless plating or vapor deposition. Therefore, the conventional joining method using solder bumps is not used, and it is not necessary to form a metal for causing solder diffusion beforehand on the inner electrodes of the chips. Cu, Ni, Au, Pt, Ag, Sn, Pb, Co and the like for example can be used for the electrodes. Furthermore, since solder bump spreading does not occur, minute connection can be attained easily, thereby being applicable to LSIs having numerous pins. Moreover, when two LSI chips are joined to each other, one of the two LSI chips is used in a wafer state, whereby low cost production is made possible.
Methods of producing the semiconductor device in accordance with claims 6, 7 and 8 have effects similar to those of claims 2, 3 and 4 respectively.